The present invention relates to an electrostatic discharge protection structure.
It is well known that semiconductor Integrated Circuits (ICs) may be damaged by Electro-Static Discharge (ESD). Four different causes are identified to be responsible for the ESD phenomenon. The first cause, due to the human body, results from electrostatic stress exerted on an IC when a human carrying electrostatic charges touches the lead pins of the IC. The second cause, due to handling by a machine, results from electrostatic discharge that occurs when a machine carrying electrostatic charges comes into contact with the lead pins of an IC. The third cause, due to charged devices, results from the ESD current spike generated when an IC's lead pins carrying electrostatic charges are grounded during the handling of the IC. The fourth cause, due to induced electric fields, results from the electric field that an IC is exposed to which may produce an ESD in the IC when the IC is later grounded.
Efforts directed at scaling down CMOS processing technologies in order to produce ICs containing transistors with thinner gate oxides and ever decreasing channel dimensions must go hand in hand with development of new structures to protect the ICs against ESD. Therefore, the need continues to exist to reliably protect deep submicron CMOS ICs from the potential damages of ESD.
A well known structure for protecting an IC against ESD damage is a Semiconductor (or Silicon) Controlled Rectifier (SCR), also known as a thyristor. FIG. 1A shows a cross-sectional view of a typical lateral SCR 10 which has an anode terminal 12 and a cathode terminal 14. FIG. 1B shows a circuit schematic representation of SCR 10. As is seen from FIG. 1B, SCR 10 is composed of an npn bipolar transistor 32, a pnp bipolar transistor 30 and two parasitic resistors 34 and 36. Pnp transistor 30 consists of p+ emitter region 20, n-well region 26 serving as base, and p-substrate region 24 serving as collector. Npn transistor 32 consists of n+ emitter region 22, p-substrate region 24 serving as base, and n-well region 26 serving as collector. Parasitic resistor 34, shown in dashed line in FIG. 1A, is connected to anode terminal 12 via n+ contact portion 27 of n-well 26. Parasitic resistor 36, likewise shown in dashed line in FIG. 1A, is connected to cathode terminal 14 via p+ contact portion 25 of p-substrate 24.
In order to turn on SCR 10, a positive voltage must be applied between anode terminal 12 and cathode terminal 14 to forward bias both transistors 30 and 32. When SCR 10 turns on, a low impedance discharge path forms between the two terminals of SCR 10 to discharge the current.
FIG. 1C shows the current-voltage characteristic of SCR 10. In FIG. 1C, the vertical axis represents the current flow between terminals, and the horizontal axis represents the voltage across terminals 12 and 14. The voltage at which SCR 10 enters the region characterized by a negative current-voltage relationship is called the snap-back or trigger voltage, which is shown in FIG. 1C as Vt.
A major disadvantage of SCR 10 is that it provides protection against ESD in only one direction, i.e., either against a positive voltage/current pulse or against a negative voltage/current pulse. Consequently, to protect an IC against ESD, one SCR must be disposed between each input/output pad of the IC and the positive supply voltage and one SCR must be disposed between each input/output pad and the negative supply voltage. Alternatively, an IC is protected against ESD damage by a SCR which provides an active discharge path in one supply direction (positive or negative) and which provides a discharge path through parasitic diodes in the other supply direction. Therefore, what is needed is a single ESD protection structure capable of protecting an IC against both positive and negative ESD pulses.
FIG. 1D shows a top view of SCR 10 constructed using conventional layout techniques. The rectangular shape of p+ region 20 or n+ region 22 is known in the art as a finger structure. When an ESD pulse appears across anode terminal 12 and cathode terminal 14, current enters into or departs from p+ region 20 and n+ region 22 from across only a single edge of each of the fingers, designated in FIG. 1D with solid arrows 40. In order to increase the current handling capability—hence to improve the ESD performance of SCR 10—prior art layout techniques add more n+ fingers in p-type substrate 24 and more p+ fingers in n-well 26. However, by thus adding more p+ and n+ fingers, a significant amount of semiconductor surface area is occupied without a proportional increase in the ESD performance of the resulting structure. This is because, the current flow between each pair of newly added p+ and n+ fingers is limited to a component crossing only a single edge of each of the added fingers. It is, therefore, advantageous to develop an ESD layout structure which provides for current flow across more edges of the p+ and n+ fingers.